In some applications, especially TV related, the system needs to capture the incoming received radio frequency data. In these applications the data rate is not constant but has small variations. The local clock needs to adjust from time to time to reliably latch this type of data. This invention deals with the problem of how to align the local clock with this incoming data.
FIG. 1 illustrates the block diagram of MPEG2 data stream transmission/reception used in digital TV satellite broadcast. Encoder 100 includes video encoder 110 and phase locked loop (PLL) 115. PLL 115 receives a stable 27 MHz reference signal generally from a piezoelectric crystal controlled oscillator (not shown) and generates encoder_CLK 117. Video encoder receives picture data 111 and encoder_CLK 117. Video encoder 110 produces an encoded data stream 113 including picture data and program clock reference information according to the MPEG2 video encoding standard.
The MPEG2 encoding standard generates picture data with varying coding densities dependent upon the particular frame data being encoded. Generally more busy frames require more data encode as compared with less busy frames. In the MPEG2 encoding standard the encoder regularly inserts a program clock reference (PCR) signal as a timestamp. The standard requires one such PCR signal at least every 100 ms for a data rate of greater than 10 Hz. Each PCR signal indicates the elapsed time in the original and decoded video stream. The use of the PCR signals will be explained below.
The encoded signal 113 is transmitted from the encoder 100 to the decoder 140. In this example the transmission is via earth orbiting satellite to an earth based receiving station. The transmission could also be by terrestrial digital radio broadcast, cablecast or storing the encoded video signal on a portable digital storage medium (DVD, Blue ray disk) and physical transportation to a suitable reader at the decoder.
Decoder 140 includes video decoder 141, time stamp processing circuit 143, voltage controlled crystal oscillator (VCXO) 145 and phase locked loop (PLL) 147. The received input signal is split. The video data to be decoded is supplied to video decoder 141. The PCR signals are supplied to time stamp processing circuit 143. Time stamp processing circuit 143 determines the deviation of the indicated time of PCR signals and the corresponding real elapsed time. VCXO 145 generates an output having small deviations in frequency from a stable 27 MHz signal generally from a piezoelectric crystal controlled oscillator (not shown) corresponding to the deviations detected by time stamp processing circuit 143. This output controls PLL 147 which supplies decoder_CLK signal 142 to video decoder 141. Decoder_CLK 142 controls the rate of decoding operation in video decoder 141. Thus decoding tracks the small deviations introduced in encoder 100. The output of video decoder 141 is picture signal 144. In the MPEG2 encoding standard decoder_CLK 142 is 27 MHz±810 Hz.
FIG. 2 illustrates a block diagram of a typical prior art technique embodying decoder 140 illustrated in FIG. 1. VCXO 145 is embodied by an external VCXO chip 202 connected to piezoelectric crystal 201. External VCXO chip 202 supplies a clock signal CLKIN 203 to an input of processing chip 210. As shown in FIG. 2, clock signal CLKIN 203 supplies PLL 211 (corresponding to PLL 147) which controls operations in processing chip 210. Processing chip 210 generates a VCXO CNTL signal 213 corresponding to the error signal produced by time stamp processing circuit 143. This is connected to a Vin input of VCXO chip 202. VCXO chip adjusts the frequency of clock signal CLKIN 203 dependent upon the voltage level of VCXO CNTL signal 213. This circuit typically also includes external capacitors 204 and 205 as shown in FIG. 2. This external VCXO chip implementation is often used to achieve the required pulling range, linearity, frequency resolution, modulation rate, slope polarity, slope sensitivity and stability needed for the application. This implementation is also often used because many vendors produce stand alone VCXO chips such as VCXO chip 202. It is also technically feasible to incorporate the circuits of VCXO chip 202 within the processing chip. This prior art technique results in extra expense for the external VCXO chip 202 or integrated circuit area needed for an internal VCXO function.